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Linux Foundation and RISC-V International launch free RISC-V training classes | ZDNet

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RISC-V, the emerging open-source instruction set processor architecture, is growing up. Sure, most of the attention has come from hardware hackers playing on RISC-V processors on development boards from companies such as SiFive. SparkFun, and BeagleBoard. There’s even a BBC Doctor Who-branded RISC-V mini-computer for kids. But, according to RISC-V CTO Mark Himelstein, RISC-V processors have already found a home in data centers and Alibaba cloud servers. So, it’s high time for classes on how to use this new open-source hardware architecture.

Thus, The Linux Foundation, the non-profit organization enabling innovation with open source, and RISC-V International, the non-profit corporation behind the RISC-V instruction set architecture (ISA), have released two new free online training courses to help you get started with the RISC-V ISA. The courses are available on edX.org.

With the recent rise of interest and deployment of RISC-V cores, systems-on-chips (SoCs), developer boards, and software and tools, there’s a real need to empower individuals to implement and use RISC-V. In order to help meet that demand, these free online courses are designed to significantly reduce the barrier to learning RISC-V skills.

The first class, Introduction to RISC-V (LFD110x), guides you through the RISC-V ecosystem, the RISC-V specifications, how to curate and develop RISC-V specifications, and the technical aspects of working with RISC-V both as a developer and end-user. The course provides you with the knowledge you’ll need to engage in the RISC-V community; contribute to the ISA specifications; and develop a wide range of RISC-V software and hardware projects. Jeffrey “Jefro” Osier-Mixon, program manager for RISC-V International, and Stephano Cetola, technical program manager for RISC-V International, developed this course. 

The second course, Building a RISC-V CPU Core (LFD111x), focuses on digital logic design and basic central processing unit (CPU) microarchitecture. In it, you’ll learn to use the Makerchip online integrated development environment (IDE). You’ll implement technologies ranging from logic gates to a simple and complete RISC-V CPU core. The class will allow participants to familiarize themselves with a variety of emerging technologies supporting an open-source hardware ecosystem, including RISC-V transaction-level verilog. Steve Hoover, founder of Redwood EDA, developed this class.
 
Calista Redmond, RISC-V International’s CEO, said in a statement: “RISC-V International is committed to providing opportunities for people to gain a deeper understanding of the RISC-V ISA and expand their skills. These courses will allow everyone to build deeper technical insight, learn more about the benefits of open collaboration, and engage with RISC-V for design freedom.”
 
You can enroll now in both Introduction to RISC-V and Building a RISC-V CPU Core. Auditing each course through edX is free for seven weeks. For $149 per class, you can opt for a paid verified certificate of completion. This also gives you access to the course for a full year and additional assessments and content to deepen their learning experience. 

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